1. Field of the Invention
The present invention-generally relates to packaging of electronic circuits and, more particularly, to the edge-mounting of integrated circuit chips at high density.
2. Description of the Prior Art
It has been recognized that substantial performance gains as well as manufacturing economies can be achieved from high integration density of electronic circuits. Short signal paths reduce signal propagation time and are less susceptible to effects of noise as well as presenting reduced resistance and capacitance to be driven by individual active circuits therein. Manufacturing economies derive from the reduced number of chips or wafers which must be subjected to lengthy and complex processes requiring expensive and specialized equipment in order to form the desired circuits.
Accordingly, technologies have been developed which provide good manufacturing yields of integrated circuits using design rules providing minimum feature size of only a fraction of a micron, allowing millions of circuit elements to be formed on a single chip. Some techniques such as sidewall image transfer (STI) allow the formation of structures which are smaller than the limit of lithographic resolution and further increases in integration density are foreseeable. However, as the number of circuit elements on a single chip is increased, manufacturing yield may be compromised and a trade-off between integration density (with commensurate performance gains and economy per chip) and overall economy of manufacture is unavoidable.
There are several other practical limitations on the amount of circuitry which may be included on a single chip and signal propagation time through a circuit element (e.g. maximum switching frequency), as well. First, there is a practical limit on chip size since a chip will usually be subjected to mechanical stresses from both accelerations and thermal cycling in normal use. Since semiconductor substrates are somewhat delicate and substrates somewhat brittle, increased chip dimensions correlate with increased likelihood of mechanical damage. As a second but related issue, each active device in the integrated circuit will produce some amount of heat which must be dissipated since elevated temperatures may cause change of the electrical properties of circuit elements on the chip. The amount of heat generally increases as cycle time is reduced and switching frequency increases. Therefore, no more active devices may be included in an integrated circuit than can be accommodated by heat transfer arrangements to maintain chip temperature in an acceptable range at the desired switching frequency of the design. Thus many circuits in which high performance is of paramount importance include cooling arrangements which may be many times the size, weight and cost of the electronic circuits themselves.
Another practical consideration in many devices is process incompatibility between various semiconductor circuit technologies. While numerous so-called hybrid technologies are known (e g. BiCMOS which provides bipolar transistors and field effect transistors of both conductivity types on the same chip) there will often be requirements for devices which cannot be economically formed on the same chip. For this and the above-noted reasons, most electronic devices will require a plurality of chips to form the complete device.
When plural chips are used, the same types of performance gains may be realized by the packaging employed in order to minimize connection length, signal propagation time, noise immunity and the like. For example, so-called multi-layer modules have been formed by lamination of sheets of polymer or ceramic to provide compact arrangements of complex connections between potentially hundreds of individual chips. However, using such modular packaging, chips are mounted in a generally coplanar manner and worst case wiring length may be up to several inches in some signal paths which, while seemingly short, may be several orders of magnitude longer than wiring on a single chip. Further, while the multi-layer module may be made of a material which is has good thermal conduction properties and may be mechanically coupled to a heat exchange structure for removing heat from the chips, heat exchange performance in combination with simpler cooling mechanisms such as convection or forced air circulation is generally very poor.
To address both wiring length and heat exchange concerns, it has been proposed to mount chips on edge. For example, "Edge-Mounted Chip Assembly for Microprocessors" by H. I. Stoller, IBM Tech. Discl. Bull.; Vol. 23, No. 5; pp. 581-582, July, 1980, describes back bonding of a master chip, such as a processor, to a substrate which carries connection pins and bonding edges of slave chips such as I/O circuits and memory chips to the front surface of the master chip by solder reflow. The slave chips may be free-standing or assembled together in a "loaf" which may also include dummy chips. The assembly is completed by placing a "hat" or can over the master and slave chips to contain thermal grease filling the space between the chips and the interior of the "hat".
However, as recognized therein, free-standing, edge-mounted chips are not as mechanically robust as the "loaf" configuration in which the chips support each other and, together, present a larger "footprint" on the master chip. In particular, under an acceleration, each free-standing slave chip is essentially cantilevered from the master chip. A practical width of each chip in comparison with a practical thickness also places the electrical connection to the edge of the chip at a mechanical disadvantage. Since the electrical bonding also provides mechanical support for the chip, fatiguing of the electrical bond which must be formed of solder may occur, compromising reliability. The mechanical load transferred to the master chip is essentially a pair of compression and tension forces in close proximity which tends to twist the master chip and may cause mechanical damage thereto.
Further, while the "loaf" configuration may also provide good temperature equalization between chips, cooling capacity is limited because of the limited surface area of the "loaf" for heat exchange and the document notes that the "loaf" configuration is preferred only if "relatively few active slave chips are required"; the remainder of the loaf being formed by dummy chips. Therefore, such a structure presents the designer with a choice between mechanical robustness and heat dissipation.
Edge-mounted chips also suffer from some other practical disadvantages due to the mechanical configuration and spatial relationships of the chips. For example, the front surface of an integrated circuit formed at high integration density is unlikely to be planar without substantial further processing and metallization to raise contacts through a relatively thick passivation layer which will support planarization. Without planarization, flatness tolerance better than 1-2 mils cannot be expected even at locations which may be designed for edge mounting of a chip. In contrast, the edge of a chip to be mounted thereon is generally formed with an optically guided diamond saw and is therefore usually highly linear. Thus, it can be understood that the edge of a chip is not particularly well-matched to the surface topography of a chip or substrate.
Planarization of the master chip also essentially precludes the formation of separate support structures on the master chip surface and which, in any event, are difficult to manufacture and to mount on the master chip surface. U.S. Pat. No. 4,992,908 to A. L. Solomon is exemplary of a complex arrangement of angled surfaces as an attempt to increase mechanical support and improve proximity of surfaces to be bonded. Another complex arrangement involving separated parallel busses is disclosed in U.S. Pat. No. 5,266,833 to D. F. Capps.
It should also be appreciated that formation of solderable connection pads on the edges of a chip is not trivial, particularly where spacing or feature size must be small to provide a sufficient number of contacts in addition to forming the edges to seat against the surface to which they are joined with sufficient proximity to allow reliable bonds to be formed. The above U.S. patent to Capps, for example, proposes disposing fine electrical wires in a rectangular grid array within a semiconductor material while the semiconductor crystal is being grown and then cut into wafers and dicing the chips from the wafer at locations coinciding with the grid array. Such a process would clearly be extremely complex, replete with exacting alignment tolerances and prohibitively expensive even if good yield could be obtained.
Therefore, manufacturing yield of the assembled package may be compromised by separations of contacts on respective chip surfaces and which must be bridged by solder (which is generally composed of soft metal) or a conductive adhesive; neither of which is well-suited to providing good mechanical support when a significant gap exists. Further, since the required volume of solder or conductive adhesive is somewhat unpredictable in view of the potential irregularity of separation between contacts on respective chip surfaces, reflow may not succeed in achieving a solder bond if insufficient solder is present or may bridge closely spaced contacts if the amount of solder is excessive and reflow is not directed by the extent of metallization or solder wettable surfaces.
Additionally, the soldering process, itself, is difficult in such structures since the bonding pads formed on the respective chips are not readily accessible for the application of heat. Therefore, it has been the practice to provide extensions on the connection pads, such as is disclosed in U.S. Pat. No. 4,266,282 to Henle et al, which limits the proximity of the edge mounted chips (e.g. precluding a "loaf" configuration) or to form the solder bonding in furnaces using complex jigs and presses and often resulting in improper bond formation.
In summary, there has been no simple arrangement for producing robust mechanical and electrical bonds for edge-mounting of chips on another chip or substrate consistent with sufficient heat dissipation for high speed integrated circuits formed at very high integration density. Further, there has been no convenient and simple process for edge-mounting of chips with high manufacturing yield.